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Amirouche OUMAZIZ’s Thesis Defense

par Laurence Laffont - publié le

Amirouche OUMAZIZ, PhD student attached to the CS-Laplace and ISGE-LAAS groups, will defend his thesis on the following subject : "Realization of integrated fuse protections on new monolithic switching cells for power converters", on Monday October 18, 2021 in the Laas conference room, at 10:30 am.

Jury :

Nathalie BATUT, Lecturer – HDR, lab. GREMAN, Tours University, rapporteur
Zoubir KHATIR, Research director, Lab. Satie, Univ. Gustave Eiffel, Marne-la-Vallée, rapporteur
Dominique PLANSON, University Professor, lab. Ampères, Lyon, external reviewer
Ayad GHANNAM, 3Dis Technologies Founder, guest
Frédéric RICHARDEAU, Abdelhakim BOURENANNANE et Emmanuel SARRAUTE, respectively thesis supervisor and co-supervisors, internal reviewers.

Abstract :

Power electronic converters are widely used in different applications requiring high reliability and availability. In order to address these requirements, the power modules have been enhanced to include features like redundancy, through fault tolerant switching cells, which allows to guarantee continuity of service. These evolved features are performed by adding electronics protections, using components like diodes, fuses, thyristors, to allow the connection of a back-up leg.

In this thesis, two power electronics integration issues are studied through design simulations and realization in order to provide more compact and secured power modules. First, fuses made of thin copper layer deposited on silicon power diodes, used in fault tolerant switching cells, are designed and simulated using finite elements methods. The idea behind is to produce auto-secured components, able to perform quick fault isolation, with very low fuses break-up energies. The second subject of this work concerns the study and development of new fully monolithic integrated switching cells on the same silicon chip. More specifically, the work deals with the integration of an inverter leg composed of IGBT (type N and P) and VDMOS (type N and P) components. For power conversion applications, the use of P-type power devices is very rare as compared to N-type power devices. This is mainly due to the poor on-state characteristics of P-type power devices as compared to their N-type counterparts. However, the association of P-type and N-type transistors, for specific applications, can make easier the monolithic integration in one chip of the phase leg.

In order to validate the suggested integration approaches, 10A/200V fuses were designed and realized by uniform copper electrolytic growth, with micrometric resolution, on silicon substrate. In order to thermally isolate the fuses constrictions from the silicon substrate, a buffer layer of epoxy has been introduced between them. The material also allows to protect the silicon chip from breakdown due to plasma arc during the fuses cut-off. When the constrictions evaporate, the fuses have to sustain the rated voltage, without important leakage current. In order to ensure this feature, a thin nitride layer is added between the fuses and the silicon substrate. Power modules provided silicone gel showed interesting results regarding the passivation of vaporized metallic particles during fuses cut-off. A generic electrothermal design approach using Comsol™ has been used to design 3D fuses models. The different fuses designs have been optimized according to their maximum allowed temperature and occupied surface. The serial and parallel configuration is the most compact fuses design, with an I2T ([A2.s]) at least five times lower compared to commercially available fuses. Once the design experimentally validated, the process is updated and reported on vertical power diodes. The proposed switching cells integration based on IGBT and VDMOS components consists on mutualizing the common backside regions of the two components in one single chip. Compared to the former work regarding converter leg integrations, this approach does not require any isolating through wall, which eases the realization process. The components design relies on an electrothermal constrain of 50 W/cm2. For a total crystal surface of 1 cm2 and for a provided cyclic ratio, the nominal current is calculated according to the electrothermal constrain. TCAD Sentaurus™ simulations, under very short turn-on times, have been conducted in order to validate the integration approach. Electrothermal transient simulations have been realized on a short-circuit converter leg in order to study the components behavior. A solution combining an IGBT and small power Mosfet is proposed and validated to avoid latch-up phenomenon during short-circuit occurrence.